(China (Mainland))
Product Summary
The 8416201CA is a 8-bit shift register, which features AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs of 8416201CA permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data of 8416201CA can be changed while CLK is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
Parametrics
8416201CA absolute maximum ratings: (1)Supply voltage range, VCC: –0.5 V to 7 V; (2)Input clamp current, IIK (VI < 0 or VI > VCC): ±20 mA; (3)Output clamp current, IOK (VO < 0 or VO > VCC): ±20 mA; (4)Continuous output current, IO (VO = 0 to VCC): ±25 mA; (5)Continuous current through VCC or GND: ±50 mA; (6)Package thermal impedance, θJA: D package: 86℃/W, N package: 80°C/W, NS package: 76℃/W, PW package: 113℃/W; (7)Storage temperature range, Tstg: –65℃ to 150℃.
Features
8416201CA features: (1)Wide Operating Voltage Range of 2 V to 6 V; (2)Outputs Can Drive Up To 10 LSTTL Loads; (3)Low Power Consumption, 80-μA Max ICC; (4)Typical tpd = 20 ns; (5)±4-mA Output Drive at 5 V; (6)Low Input Current of 1 μA Max; (7)AND-Gated (Enable/Disable) Serial Inputs; (8)Fully Buffered Clock and Serial Inputs; (9)Direct Clear.
Diagrams
 |
 841602AGILF |
Other |
|
Data Sheet |
Negotiable |
|
||||||||||||
|
841602AGILFT |
Other |
|
Data Sheet |
Negotiable |
|
||||||||||||
|
841604AGILF |
Other |
|
Data Sheet |
Negotiable |
|
||||||||||||
|
841604AGILFT |
Other |
|
Data Sheet |
Negotiable |
|
||||||||||||
|
841608AKI |
Other |
|
Data Sheet |
Negotiable |
|
||||||||||||
 |
841608AKILF |
IDT |
Clock Synthesizer / Jitter Cleaner PCIe, sRIO HSCL 8Out FemtClk Gener. |
Data Sheet |
|
|
||||||||||||
